Category Archives: VHDL Lab Programming Tutorials

HDL Code To Simulate Full Adder

By | December 3, 2017

HDL Code To Simulate Full Adder Aim –Simulate Full Adder Basic concepts to understand simulate full adder Basics of Verilog Code  Full Adder Theory Verilog Code For Data Flow Modeling Verilog Code module fa2( input a,b,c, output s,cout ); assign s=(a^b^c); assign cout=(a & b)| (b & c)| (c & a); endmodule In data flow modelling,… Read More »

HDL Code To Simulate 1-Bit Comparator

By | December 3, 2017

HDL Code To Simulate 1-Bit Comparator Aim –Simulate 1-Bit Comparator Basic concepts to understand simulate 1-bit comparator   1-Bit Comparator Theory Input – a ( 1bit binary 1 or 0), b( 1bit binary 1 or 0) . Output- l, e, g. l=1 when a=0, b=1. e=1 for two conditions, a=0  b=1, a=1 and b=1. g=1 when a=1, … Read More »

HDL Code To Simulate 8:3 Priority Encoder

By | November 30, 2017

HDL code to simulate 8:3 priority encoder Aim –Simulate 8:3 priority encoder  Basic concepts to understand simulate 8:3 priority encoder Priority Encoder Theory In priority encoder, there are 8 inputs, 1 enable signal and 3 outputs. In this program, we are using [7:0]i==i[7], i[6], i[5], i[4], i[3], i[2], i[1], i[0] as inputs. en – enable signal [2:0]y… Read More »

HDL Code To Simulate 4-bit Binary To Gray Converter

By | November 29, 2017

HDL code to simulate 4-bit binary to gray converter Aim- Simulate 4-bit binary to gray converter using HDL code. Basics of 4-bit binary to gray converter what is gray code? A Gray Code represents binary encoded number constitutes a sequence of bits such that only one bit in the group changes from before and after.… Read More »

HDL Code To Simulate 2:4 Decoder

By | November 28, 2017

HDL code to simulate 2:4 Decoder Aim – Simulate of 2:4 Decoder using HDL code. Basics of 2:4 Decoder to learn simulate 2:4 decoder 2:4 Decoder has 2 inputs and 4 outputs. In this program, a,b are two inputs and y0,y1,y2,y3 are four outputs. en– enable should be active high, in order to get output.… Read More »

HDL Code To Simulate All Logic Gates

By | November 28, 2017

HDL Code To Simulate All Logic Gates Aim – Simulation of all logic gates using HDL code. Basics Of Logic Gates   Input- a,b Output-c(and), d(or), e(xor), f(not_a), g(nand), h(nor), i(xnor) Verilog Code module logicgates( input a,b, output c,d,e,f,g,h,i); assign c= a & b; assign d= a|b; assign e= a^b; assign f= ~a; assign g=… Read More »