HDL Code To Simulate 1:4 Demux

By | November 29, 2017
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HDL code to simulate 1:4 Demux | Verilog code to simulate 1:4 Demux

Aim – Simulate 1:4 Demux using HDL code.

Basics of 4: 1 Mux learn to simulate 1:4  Demux

  1. 1:4 Demux has 1 inputs and 4 output. There are 2 select lines.
  2. In this program, 4 outputs are y3,y2,y1,y0.
  3. 2 select lines are s0, s1.
  4. Only one input i. Input i is always 1.
  5. Depending upon the value of the select line, outputs are formed.

Truth Table

simulate 1:4 demux truth tableHDL Program To simulate 4:1 mux


Verilog Code

module demux(
input s1,s0,I,en,
output y3,y2,y1,y0
assign y0=(~s1)&(~s0)& I& ~en;
assign y1=(~s1)& s0& I& ~en;
assign y2=s1&(~s0)& I & ~en;
assign y3=s1& s0 & I & ~en;

Verilog Test Bench

module demux_tb;
reg s1;reg s0;
reg I;reg en;
wire y3;wire y2;
wire y1;wire y0;
demux uut (.s1(s1), .s0(s0), .I(I),
.en(en), .y3(y3), .y2(y2),
.y1(y1), .y0(y0));

s1 = 0;s0 = 0;I = 1;en = 0;#100;
s1 = 0;s0 = 1;I = 1;en = 0;#100;
s1 = 1;s0 = 0;I = 1;en = 0;#100;
s1 = 1;s0 = 1;I = 1;en = 0;#100;

simulate 1:4 demux o/p


Related Blogs

Basics of 1:4 Demultiplexer

Simulation of 4:1 Multiplexer and 1:4 Demultiplexer using Verilog code.

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HDL code to simulate 4:1 Mux

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HDL Code To Simulate All Logic Gates


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