HDL Code To Simulate 32-Bit ALU

By | December 6, 2017
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HDL Code To Simulate 32-Bit ALU

Aim –Simulate 32-Bit ALU

Basic concepts to understand simulate full adder

simulate 32-bit ALU

Verilog Code to simulate 32-Bit ALU

Verilog Code

module alu(
input [3:0] a,b,s,
input en,
output reg[7:0] y
);
always@( a, b, s, en, y )
begin
if(en==1)
begin
case (s)
4'd0: y=a+b;
4'd1: y=a-b;
4'd2: y=a*b;
4'd3: y={4'd0, ~a};
4'd4: y={4'd0, (a & b)};
4'd5: y={4'd0, (a | b)};
4'd6: y={4'd0, (a ^ b)};
4'd7: y={4'd0, ~(a & b)};
4'd8: y={4'd0, ~(a | b)};
4'd9: y={4'd0, ~(a ^ b)};
default: y=8'b00000000;
endcase
end
else
y=8'b00000000;
end
endmodule

Verilog Code Explanation

  • Level of abstraction used in this program – Behavioral Modeling.
   
always @(en,s,a,b);    // sensitivity lists are en,s,a,b because output depends upon these values
                //initially,  we are checking the value of enable signal, if en=1, then only the output is produced otherwise the output is               zero.
if( en==1)                                            
begin
case(s)                              // we are using case statements because of multiple conditions// control expression is 's' because depending upon that value, particular operation takes place
//
4'd0: y=a+b;                         // 4'd0 = 4'b0000 i.e when s=0000 then y= a+b
4'd1: y=a-b;
4'd2: y=a*b;
4'd3: y={4'd0,~a};
4'd4: y={4'd0,(a&b)};                 {} used for concatanation
4'd5: y={4'd0,(a|b)};
4'd6: y={4'd0,(a^b)};
4'd7: y={4'd0,~(a&b)};
4'd8: y={4'd0,~(a|b)};
4'd9: y={4'd0,~(a^b)};
default: y=8'b00000000;              // when select line specified is other than 0 to9
endcase
end
else
y=8'b00000000;                       // if en=0
end
endmodule
Verilog Test Bench To Simulate 32-Bit ALU
Verilog Test Bench

module alut1;
reg [3:0] a;
reg [3:0] b;
reg [3:0] s;
reg en;
wire [7:0] y;

alu uut (
.a(a),
.b(b),
.s(s),
.en(en),
.y(y));
initial begin
a = 0;
b = 0;
s = 0;
en = 0;

#100;
a=1;b=5; s=3;en=1; #10;
a=5;b=9; s=2;en=1; #10;
a=5;b=6; s=4;en=1; #10;
a=4;b=1; s=0;en=1; #10;
a=3;b=2; s=6;en=1; #10;
end
endmodule
Verilog Test Bench Explanation
// Initialize Input
                   // select line selected and givig a, en ,b values.. output can seen in simulate behavioral model
s = 0;a = 7;b = 2;en = 1;#100;// select line selcted is 0 i.e s=0000 then addition y=a+b is performed. In behavioral model for s=0000, you should get y=a+b=7+2=9 i.e 00001001

Output

simulate 32-bit ALU

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Category: Electronics VHDL Lab Programming Tutorials

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