HDL Code To Simulate 4:1 Mux

By | November 29, 2017
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HDL code to simulate 4:1 Mux

Aim – Simulate 4:1 Mux using HDL code.

Basics of 4: 1 Mux to learn simulate 4:1 Mux

  1. 4:1 Mux has 4 inputs and 1 output. There are 2 select lines.
  2. In this program, 4 inputs are i3,i2,i1,i0.
  3. 2 select lines are sel[0], sel[1].
  4. Only one output y.
  5. Depending upon the value of the select line, the input is passed to the output.

Truth Table

simulate 4:1 mux truth table

HDL Program To simulate 4:1 mux
Verilog Code
module mux41(
input [3:0] i,
input [1:0] sel,
output y
);

assign y= ((~ sel[0] )& (~ sel[1]) & i[3])|
(~sel[0] & sel[1] & i[2]) |
(sel[0] & ~sel[1] & i[1]) |
(sel[0] & sel[1] & i[0]) ;
endmodule
Verilog Test Bench

module mux4_1;
reg [3:0] i;
reg [1:0] sel;
wire y;
mux41 uut (.i(i), .sel(sel), .y(y));
initial begin
i = 8;sel = 0;#100;
i = 4;sel = 1;#100;
i = 2;sel = 2;#100;
i = 1;sel = 3;#100;
#100;
end
endmodule

Output

simulate 4:1 mux output

 

DOWNLOAD VERILOG PROGRAMS(SECURE DOWNLOAD)

Related Blogs

Basics of 4:1 Mux

VHDL 4:1 Multiplexer

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