HDL Code To Simulate All Logic Gates

By | November 28, 2017
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HDL Code To Simulate All Logic Gates

Aim – Simulation of all logic gates using HDL code.

Basics Of Logic Gatesall logic gate symbols,simulation

logicgates TruthTable Simulation

 

Input- a,b

Output-c(and), d(or), e(xor), f(not_a), g(nand), h(nor), i(xnor)

Verilog Code

module logicgates( input a,b,
output c,d,e,f,g,h,i);
assign c= a & b;
assign d= a|b;
assign e= a^b;
assign f= ~a;
assign g= ~(a&b);
assign h= ~(a|b);
assign i= ~(a^b);
endmodule
Verilog Test Bench

module logic_tb;
reg a; reg b;
wire c,d,e,f,g,h,i;
logicgates uut ( .a(a), .b(b), .c(c),
.d(d), .e(e), .f(f), .g(g), .h(h), .i(i));
initial
begin
a = 0;b = 0;#100;
a = 0;b = 1;#100;
a = 1;b = 0;#100;
a = 1;b = 1;#100;
end
endmodule

Output

simulation results

Related Blogs

Digital Logic Gates Summary 

Basic Logic Gates With Truth Table

Verilog Code For Basic Gates

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