Tag Archives: HDL Code

HDL Code To Simulate All Logic Gates

By | November 28, 2017

HDL Code To Simulate All Logic Gates Aim – Simulation of all logic gates using HDL code. Basics Of Logic Gates   Input- a,b Output-c(and), d(or), e(xor), f(not_a), g(nand), h(nor), i(xnor) Verilog Code module logicgates( input a,b, output c,d,e,f,g,h,i); assign c= a & b; assign d= a|b; assign e= a^b; assign f= ~a; assign g=… Read More »