Tag Archives: Verilog Code To Simulate 1-bit Comparator

HDL Code To Simulate 1-Bit Comparator

By | December 3, 2017

HDL Code To Simulate 1-Bit Comparator Aim –Simulate 1-Bit Comparator Basic concepts to understand simulate 1-bit comparator   1-Bit Comparator Theory Input – a ( 1bit binary 1 or 0), b( 1bit binary 1 or 0) . Output- l, e, g. l=1 when a=0, b=1. e=1 for two conditions, a=0  b=1, a=1 and b=1. g=1 when a=1, … Read More »