Tag Archives: VHDL Simulation

HDL Code To Simulate 2:4 Decoder

By | November 28, 2017

HDL code to simulate 2:4 Decoder Aim – Simulate of 2:4 Decoder using HDL code. Basics of 2:4 Decoder to learn simulate 2:4 decoder 2:4 Decoder has 2 inputs and 4 outputs. In this program, a,b are two inputs and y0,y1,y2,y3 are four outputs. en– enable should be active high, in order to get output.… Read More »

Free Download Executed Engineering VHDL Lab Programs

By | November 28, 2017

FREE DOWNLOAD EXECUTED VHDL LAB PROGRAMS ( ENGINEERING ECE) This file includes VHDL lab programs,  HDL code to Realise Logic Gates. HDL code to simulate and implement 2:4 Decoder. HDL code to simulate and implement 4:1 Mux. HDL code to simulate and implement 1:4 Demux. HDL code to simulate and implement Binary to Gray Converter. HDL code… Read More »